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| DATASHEET 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 ICSSSTUAF32866C design of the ICSSSTUAF32866C must ensure that the outputs will remain low, thus ensuring no glitches on the output. The device monitors both DCS and CSR inputs and will gate the Qn outputs from changing states when both DCS and CSR inputs are high. If either DCS and CSR input is low, the Qn outputs will function normally. The RESET input has priority over the DCS and CSR control and will force the outputs low. If the DCS-control functionality is not desired, then the CSR input can be hardwired to ground, in which case, the setup-time requirement for DCS would be the same as for the other D data inputs. Package options include 96-ball LFBGA (MO-205CC). Description This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8-V CMOS drivers that have been optimized to drive the DDR-II DIMM load. ICSSSTUAF32866C operates from a differential clock (CLK and CLK). Data are registered at the crossing of CLK going high, and CLK going low. The C0 input controls the pinout configuration of the 1:2 pinout from A configuration (when low) to B configuration (when high). The C1 input controls the pinout configuration from 25-bit 1:1 (when low) to 14-bit 1:2 (when high). A - Pair Configuration (C01 = 0, C11 = 1 and C02 = 0, C12 = 1) Parity that arrives one cycle after the data input to which it applies is checked on the PAR_IN of the first register. The second register produces to PPO and QERR signals. The QERR of the first register is left floating. The valid error information is latched on the QERR output of the second register. If an error occurs QERR is latched low for two cycles or until RESET is low. B - Single Configuration (C0 = 0, C1 = 0) The device supports low-power standby operation. When the RESET input (RESET) is low, the differential input receivers are disabled, and undriven (floating) data, clock and reference voltage (VREF) inputs are allowed. In addition, when RESET is low all registers are reset, and all outputs are forced low. The LVCMOS RESET and Cn inputs must always be held at a valid logic high or low level. To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low state during power up. In the DDR-II RDIMM application, RESET is specified to be completely asynchronous with respect to CLK and CLK. Therefore, no timing relationship can be guaranteed between the two. When entering reset, the register will be cleared and the outputs will be driven low quickly, relative to the time to disable the differential input receivers. However, when coming out of reset, the register will become active quickly, relative to the time to enable the differential input receivers. As long as the data inputs are low, and the clock is stable during the time from the low-to-high transition of RESET until the input receivers are fully enabled, the Features * 25-bit 1:1 or 14-bit 1:2 registered buffer with parity check functionality * Supports SSTL_18 JEDEC specification on data inputs and outputs * Supports LVCMOS switching levels on C0, C1, and RESET inputs * Low voltage operation: VDD = 1.7V to 1.9V * Drop-in replacement for ICSSSTUA32864 * Available in 96-ball BGA package Applications * DDR2 Memory Modules * Provides complete DDR DIMM solution with * ICS98ULPA877A or IDTCSPUA877A Ideal for DDR2 400, 533, and 667 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 1 ICSSSTUAF32866C 7100/9 ICSSSTUAF32866C 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Functional Block Diagram for 1:1 Mode (Positive Logic) RESET CLK CLK VREF DCKE D C1 R QCKEA DODT D C1 R QOTDA DCS 1D C1 R QCSA CSR D1 O 1 1D C1 R Q1A (1) Q1B TO 21 OTHER CHANNELS NOTE: 1. Disabled in 1:1 configuration. 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 2 ICSSSTUAF32866C 7100/9 ICSSSTUAF32866C 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Functional Block Diagram for 1:2 Mode (Positive Logic) RESET CLK CLK VREF DCKE 1D C1 R QCKEA QCKEB (1) DODT 1D C1 R QODTA QODTB (1) DCS 1D C1 R QCSA QCSB (1) CSR D1 0 1 1D C1 R Q1B Q1A (1) TO 10 OTHER CHANNELS (D2-D6, D8-D10, D12-D13) NOTE: 1. Disabled in 1:1 configuration. 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 3 ICSSSTUAF32866C 7100/9 ICSSSTUAF32866C 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Pin Configurations 14 BIT 1:2 REGISTERS 1 A B C D E F DCKE D2 D3 DODT D5 D6 2 PPO NC NC QERR NC NC 3 VREF GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VREF 4 VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VDD 5 6 A B C D E F 1 D1 D2 D3 D4 D5 D6 2 PPO NC NC QERR NC NC 3 VREF GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VREF 4 VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VDD 5 Q1A Q2A Q3A Q4A Q5A Q6A C1 QCSA ZOH Q8A Q9A Q10A 6 Q1B Q2B Q3B Q4B Q5B Q6B C0 QCSB ZOL Q8B Q9B Q10B QCKEA QCKEB Q2A Q3A Q2B Q3B QODTA QODTB Q5A Q6A C1 QCSA ZOH Q8A Q9A Q10A Q11A Q12A Q13A Q14A Q5B Q6B C0 QCSB ZOL Q8B Q9B Q10B Q11B Q12B Q13B Q14B G PAR_IN RESET H J K L M N P R T CLK CLK D8 D9 D10 D11 D12 D13 D14 DCS CSR NC NC NC NC NC NC NC G PAR_IN RESET H J K L M N P R T CLK CLK D8 D9 D10 DODT D12 D13 DCKE DCS CSR NC NC NC NC NC NC NC QODTA QODTB Q12A Q13A Q12B Q13B QCKEA QCKEB REGISTER A (C0 = 0, C1 = 1) 25 BIT 1:1 REGISTER 1 A B C D E F DCKE D2 D3 DODT D5 D6 REGISTER B (C0 = 1, C1 = 1) 2 PPO D15 D16 QERR D17 D18 3 VREF GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VREF 4 VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VDD 5 QCKE Q2 Q3 QODT Q5 Q6 C1 QCS ZOH Q8 Q9 Q10 Q11 Q12 Q13 Q14 6 NC Q15 Q16 NC Q17 Q18 C0 NC ZOL Q19 Q20 Q21 Q22 Q23 Q24 Q25 G PAR_IN RESET H J K L M N P R T CLK CLK D8 D9 D10 D11 D12 D13 D14 DCS CSR D19 D20 D21 D22 D23 D24 D25 C0 = 0, C1 = 0 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 4 ICSSSTUAF32866C 7100/9 ICSSSTUAF32866C 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE 96 Ball LFBGA Package Attributes 6 5 4 3 2 1 A B C D E F G H J K L M N P R T Top Marking TOP VIEW A B C D E F G H J K L M N P R T 1 2 3 4 5 6 BOTTOM VIEW SIDE VIEW 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 5 ICSSSTUAF32866C 7100/9 ICSSSTUAF32866C 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Function Table Inputs1 RESET H H H H H H H H H H H H L 1 Outputs CLK L or H L or H L or H L or H DCS L L L L L L H H H H H H X or Floating CSR L L L H H H L L L H H H CLK L or H L or H L or H L or H Dn, DODT, DCKE L H X L H X L H X L H X X or Floating Qn L H Q 02 L H Q0 L H Q0 2 2 QCS L L Q02 L L Q0 H H Q0 H H Q0 L 2 2 2 QODT, QCKE L H Q02 L H Q02 L H Q02 L H Q02 L Q 02 Q 02 Q0 L 2 X or X or X or Floating Floating Floating 2 H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care = LOW to HIGH = HIGH to LOW Output level before the indicated steady-state conditions were established. 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 6 ICSSSTUAF32866C 7100/9 ICSSSTUAF32866C 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Parity and Standby Function Table Inputs1 RESET H H H H H H H H H H L 1 Outputs of Inputs = H (D1 - D25) Even Odd Even Odd Even Odd Even Odd X X X or Floating DCS L L L L X X X X H X X or Floating CSR X X X X L L L L H X X or Floating CLK L or H X or Floating CLK L or H X or Floating PAR_IN2 L L H H L L H H X X X or Floating PPO L H H L L H H L PPO0 PPO0 L QERR3 H L L H H L L H QERR0 QERR0 H H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care = LOW to HIGH = HIGH to LOW Data Inputs = D2, D3, D5, D6, D8 - D25 when C0 = 0 and C1 = 0. Data Inputs = D2, D3, D5, D6, D8 - D14 when C0 = 0 and C1 = 1. Data Inputs = D1 - D6, D8 - D10, D12, D13 when C0 = 1 and C1 = 1. 2 PAR_IN arrives one clock cycle after the data to which it applies when C0 = 0, and two clock cycles when C0 = 1. 3 This transition assumes QERR is HIGH at the crossing of CLK going HIGH and CLK going LOW. If QERR is LOW, it stays latched LOW for two clock cycles or until RESET is driven LOW. 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 7 ICSSSTUAF32866C 7100/9 ICSSSTUAF32866C 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Logic Diagram (1:1) G2 RESET H1 J1 CLK CLK D2 - D3, D5 - D6, D8 - D25 VREF LPS0 (Internal Node) 22 A3, T3 D CE CE CLK Q 22 D2 - D3, D5 - D6, D8 - D25 22 Q2 - Q3, Q5 - Q6, Q8 - Q25 R 22 D2 - D3, D5 - D6, D8 - D25 Parity Check C1 G5 0 D CLK R Q 1 D CLK R CE Q D CLK R Q A2 PPO 1 0 PAR_IN G1 D2 QERR C0 G6 CLK 2-Bit Counter R LPS1 (Internal Node) 0 D Q CLK R 1 Parity Logic Diagram for 1:1 Register Configuration (Positive Logic); C0 = 0, C1 = 0 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 8 ICSSSTUAF32866C 7100/9 ICSSSTUAF32866C 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Logic Diagram (1:2) G2 RESET H1 J1 CLK CLK D2 - D3, D5 - D6, D8 - D14 VREF LPS0 (Internal Node) 11 A3, T3 D CE CE CLK Q 11 D2 - D3, D5 - D6, D8 - D14 11 Q2A - Q3A, Q5A - Q6A, Q8A - Q14A Q2B - Q3B, Q5B - Q6B, Q8B - Q14B 11 R 11 D2 - D3, D5 - D6, D8 - D14 Parity Check C1 G5 0 D CLK R Q 1 D CLK R CE Q D CLK R Q A2 PPO 1 0 PAR_IN G1 D2 QERR C0 G6 CLK 2-Bit Counter R LPS1 (Internal Node) 0 D Q CLK R 1 Parity Logic Diagram for 1:2 Register - A Configuration (Positive Logic); C0 = 0, C1 = 1 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 9 ICSSSTUAF32866C 7100/9 ICSSSTUAF32866C 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Logic Diagram (1:2) G2 RESET H1 J1 CLK CLK LPS0 (Internal Node) D1 - D6, D8 - D13 VREF A3, T3 11 D CE CE CLK Q 11 D1 - D6, D8 - D13 11 Q1A - Q6A, Q8A - Q13A Q1B - Q6B, Q8B - Q13B 11 R 11 D1 - D6, D8 - D13 Parity Check C1 G5 0 D CLK R Q 1 D CLK R CE Q D CLK R Q A2 PPO 1 0 PAR_IN G1 D2 QERR C0 G6 CLK 2-Bit Counter R LPS1 (Internal Node) 0 D Q CLK R 1 Parity Logic Diagram for 1:2 Register - B Configuration (Positive Logic); C0 = 1, C1 = 1 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 10 ICSSSTUAF32866C 7100/9 ICSSSTUAF32866C 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Absolute Maximum Ratings Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Item Supply Voltage, VDD Input Voltage Range, VI Output Voltage Range, 1 Rating -0.5V to 2.5V -0.5V to 2.5V -0.5V to VDD + 0.5V 50mA 50mA 50mA 100mA 70.9C/W 65C/W -65 to +150C 0m/s Airflow 1m/s Airflow VO1,2 Input Clamp Current, IIK Output Clamp Current, IOK Continuous Output Clamp Current, IO Continuous Current through each VDD or GND Package Thermal Impedance (ja)3 Storage Temperature 1 The input and output negative voltage ratings may be exceeded if the ratings of the I/P and O/P clamp current are observed. 2 This current will flow only when the output is in the high state level VO > VDDQ. 3 The package thermal impedance is calculated in accordance with JESD 51. 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 11 ICSSSTUAF32866C 7100/9 ICSSSTUAF32866C 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Terminal Functions Terminal Name GND VDD VREF ZOH ZOL CLK CLK C0, C1 RESET CSR, DCS D1 - D25 DODT DCKE Q1 - Q25 QCS QODT QCKE PPO PAR_IN QERR Electrical Characteristics Ground Input 1.8V nominal 0.9V nominal Input Input Differential Input Differential Input LVCMOS Input LVCMOS Input SSTL_18 Input SSTL_18 Input SSTL_18 Input SSTL_18 Input 1.8V CMOS 1.8V CMOS 1.8V CMOS 1.8V CMOS 1.8V CMOS SSTL_18 Input Open Drain Output Ground Power Supply Voltage Input Reference Clock Reserved for future use Reserved for future use Description Positive Master Clock Input Negative Master Clock Input Configuration Control Inputs Asynchronous Reset Input. Resets registers and disables VREF data and clock differential-input receivers. Chip Select Inputs. Disables outputs D1 - D24 output switching when both inputs are HIGH. Data Input. Clocked in on the crossing of the rising edge of CLK and the falling edge of CLK. The outputs of this register bit will not be suspended by the DCS and CSR controls The outputs of this register bit will not be suspended by the DCS and CSR controls Data Outputs that are suspended by the DCS and CSR controls Data Output that will not be suspended by the DCS and CSR controls Data Output that will not be suspended by the DCS and CSR controls Data Output that will not be suspended by the DCS and CSR controls Partial Parity Output. Indicates off parity of D1 - D25 Parity Input arrives one cycle after corresponding data input Output Error bit, generated one cycle after the corresponding data output 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 12 ICSSSTUAF32866C 7100/9 ICSSSTUAF32866C 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Operating Characteristics The RESET and Cn inputs of the device must be held at valid levels (not floating) to ensure proper device operation. The differential inputs must not be floating unless RESET is LOW. Symbol VDDQ VREF VTT VI VIH VIL VIH VIL VIH VIL VICR VID IOH IOL IERROL TA Parameter I/O Supply Voltage Reference Voltage Termination Voltage Input Voltage AC High-Level Input Voltage Data, CSR, AC Low-Level Input Voltage and PAR_IN DC High-Level Input Voltage inputs DC Low-Level Input Voltage High-Level Input Voltage Low-Level Input Voltage Common Mode Input Range Differential Input Voltage High-Level Output Current Low-Level Output Current QERR LOW Level Output Current Operating Free-Air Temperature RESET, C0, C1 CLK, CLK Min. 1.7 0.49 * VDD VREF - 0.04 0 VREF + 0.25 Typ. 0.5 * VDD VREF Max. 1.9 0.51 * VDD VREF + 0.04 VDD VREF - 0.25 Units V V V V VREF + 0.125 VREF - 0.125 0.65 * VDDQ 0.35 * VDDQ 0.675 600 -8 8 25 0 +70 1.125 V V V mV mA mA C 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 13 ICSSSTUAF32866C 7100/9 ICSSSTUAF32866C 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE DC Electrical Characteristics Over Operating Range Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0C to +70C, VDD = 1.7V to 1.9V. Symbol VIK VOH VOL VERROL IIL Output HIGH Voltage Output LOW Voltage QERR Output LOW Voltage All Inputs Static Standby Parameter Test Conditions II = -18mA IOH = -6mA IOL = 6mA IERROL = 25mA, VDD = 1.7V VI = VDD or GND; VDD = 1.9V IO = 0, VDD = 1.9V, RESET = GND IO = 0, VDD = 1.9V, RESET = VDD, VI = VIH(AC) or VIL(AC), CLK = CLK = VIH(AC) or VIL(AC) IO = 0, VDD = 1.9V, RESET = VDD, VI = VIH(AC) or VIL(AC), CLK = VIH(AC), CLK = VIL(AC) IO = 0, VDD = 1.8V, RESET = VDD, VI = VIH(AC) or VIL(AC), CLK and CLK switching 50% duty cycle IO = 0, VDD = 1.8V, RESET = VDD, VI = VIH(AC) or VIL(AC), CLK and CLK switching 50% duty cycle. One data input switching at half clock frequency, 50% duty cycle. VI = VREF 350mV VICR = 1.25V, VIPP = 360mV VI = VDD or GND 1:1 mode 1:2 mode Min. 1.2 Typ. Max. -1.2 0.5 0.5 Units V V V V A A -5 +5 100 10 IDD Static Operating mA 90 A/Clock MHz A/Clock MHz/ Data Input 3 3 5 pF Dynamic Operating (clock only) IDDD Dynamic Operating (per each data input) 210 65 120 2 2 Data Inputs CIN CLK and CLK RESET 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 14 ICSSSTUAF32866C 7100/9 ICSSSTUAF32866C 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Timing Requirements Over Recommended Operating Free-Air Temperature Range VDD = 1.8V 0.1V Symbol fCLOCK tW tACT 1 2 Parameter Clock Frequency Pulse Duration, CLK, CLK HIGH or LOW Differential Inputs Active Time Differential Inputs Inactive Time DCS before CLK, CLK, CSR HIGH; CSR before CLK, CLK, DCS HIGH Min. 1 Max. 410 10 15 Units MHz ns ns ns tINACT 0.7 0.5 0.5 0.5 0.5 0.5 ns ns tSU Setup Time DCS before CLK, CLK, CSR LOW DODT, DOCKE, and data before CLK, CLK PAR_IN before CLK, CLK DCS, DODT, DCKE, and data after CLK, CLK PAR_IN after CLK, CLK tH Hold Time 1 VREF must be held at a valid input voltage level and data inputs must be held at valid logic levels for a minimum time of tACT(max) after RESET is taken HIGH. 2 VREF, data, and clock inputs must be held at a valid input voltage levels (not floating) for a minimum time of tINACT(max) after RESET is taken LOW. Switching Characteristics Over Recommended Free Air Operating Range (unless otherwise noted) VDD = 1.8V 0.1V Symbol fMAX tPDM tPDMSS tPD tLH tHL tPHL tPLH Parameter Max Input Clock Frequency Propagation Delay, single bit switching, CLK to CLK to Qn Propagation Delay, simultaneous switching, CLK to CLK to Qn Propagation Delay, CLK and CLK to PPO LOW to HIGH Propagation Delay, CLK to CLK to QERR HIGH to LOW Propagation Delay, CLK to CLK to QERR HIGH to LOW Propagation Delay, RESET to PPO to Qn LOW to HIGH Propagation Delay, RESET to QERR Min. 410 1.3 0.5 1.2 1 Max. 1.9 2 1.7 3 2.4 3 3 Units MHz ns ns ns ns ns ns ns 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 15 ICSSSTUAF32866C 7100/9 ICSSSTUAF32866C 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Output Buffer Characteristics Output edge rates over recommended operating free-air temperature range VDD = 1.8V 0.1V Parameter dV/dt_r dV/dt_f dV/dt_ 1 1 Min. 1 1 Max. 4 4 1 Units V/ns V/ns V/ns Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate). 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 16 ICSSSTUAF32866C 7100/9 ICSSSTUAF32866C 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Register Timing RESET DCS CSR n CLK n +1 n+2 n+3 n+4 CLK tACT (1) tSU tH D1 - D25 tPDM, tPDMSS CLK to Q Q1 - Q25 tSU (1) tH PARIN tPD CLK to PPO PPO tPHL CLK to QERR (2) tPHL, tPLH CLK to QERR QERR Data to QERR Latency H, L, or X H or L Timing Diagram for SSTUAF32866C Used as a Single Device; C0 = 0, C1 = 0, RESET Switches from L to H NOTES: 1.After RESET is switched from LOW to HIGH, all data and PAR_IN inputs signals must be set and held low for a minimum time of tACTMAX, to avoid false error. 2.If the data is clocked in on the n clock pulse, the QERR output signal will be generated on the n+2 clock pulse, and it will be valid on the n+3 clock pulse. 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 17 ICSSSTUAF32866C 7100/9 ICSSSTUAF32866C 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Register Timing Timing Diagram for the First SSTUAF32866C Used as a Single Device; C0 = 0, C1 = 0, RESET Held HIGH NOTE: 1.If the data is clocked in on the n clock pulse, the QERR output signal will be generated on the n+2 clock pulse, and it will be valid on the n+3 clock pulse. If an error occurs and the QERR output is driven low, it stays latched low for a minimum of two clock cycles or until RESET is driven low. 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 18 ICSSSTUAF32866C 7100/9 ICSSSTUAF32866C 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Register Timing RESET tINACT DCS (1) (1) CSR CLK (1) CLK (1) (1) D1 - D25 tRPHL RESET to Q Q1 - Q25 (1) PARIN tRPHL RESET to PPO PPO QERR tRPLH RESET to QERR H, L, or X H or L Timing Diagram for SSTUAF32866C Used as a Single Device; C0 = 0, C1 = 0, RESET Switches from H to L NOTE: 1.After RESET is switched from HIGH to LOW, all data and clock inputs signals must be set and held at valid logic levels (not floating) for a minimum time of tINACTMAX. 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 19 ICSSSTUAF32866C 7100/9 ICSSSTUAF32866C 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Register Timing RESET DCS CSR n CLK n +1 n+2 n+3 n+4 CLK tACT (1) tSU tH D1 - D14 tPDM, tPDMSS CLK to Q Q1 - Q14 tSU (1) tH PARIN tPD CLK to PPO PPO tPHL CLK to QERR (2) tPHL, tPLH CLK to QERR QERR (not used) Data to QERR Latency H, L, or X H or L Timing Diagram for the First SSTUAF32866C (1:2 Register-A Configuration) Device Used in a Pair; C0 = 0, C1 = 1, RESET Switches from Lto H NOTES: 1.After RESET is switched from LOW to HIGH, all data and PAR_IN inputs signals must be set and held low for a minimum time of tACTMAX, to avoid false error. 2.If the data is clocked in on the n clock pulse, the QERR output signal will be generated on the n+1 clock pulse, and it will be valid on the n+2 clock pulse. . 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 20 ICSSSTUAF32866C 7100/9 ICSSSTUAF32866C 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Register Timing Timing Diagram for the First SSTUAF32866C (1:2 Register-A Configuration) Device Used in a Pair; C0 = 0, C1 = 1, RESET Held HIGH NOTE: 1.If the data is clocked in on the n clock pulse, the QERR output signal will be generated on the n+1 clock pulse, and it will be valid on the n+2 clock pulse. If an error occurs and the QERR output is driven low, it stays latched low for a minimum of two clock cycles or until RESET is driven low. 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 21 ICSSSTUAF32866C 7100/9 ICSSSTUAF32866C 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Register Timing RESET tINACT DCS (1) (1) CSR CLK (1) CLK (1) (1) D1 - D14 tRPHL RESET to Q Q1 - Q14 (1) PARIN tRPHL RESET to PPO PPO QERR (not used) tRPLH RESET to QERR H, L, or X H or L Timing Diagram for the First SSTUAF32866C (1:2 Register-A Configuration) Device Used in a Pair; C0 = 1, C1 = 1; RESET Switches from H to L NOTE: 1.After RESET is switched from HIGH to LOW, all data and clock inputs signals must be set and held at valid logic levels (not floating) for a minimum time of tINACTMAX. 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 22 ICSSSTUAF32866C 7100/9 ICSSSTUAF32866C 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Register Timing RESET DCS CSR n CLK n +1 n+2 n+3 n+4 CLK tACT (1) tSU tH D1 - D14 tPDM, tPDMSS CLK to Q Q1 - Q14 tSU (1,2) tH PARIN tPD CLK to PPO PPO (not used) tPHL CLK to QERR (3) tPHL, tPLH CLK to QERR QERR Data to QERR Latency H, L, or X H or L Timing Diagram for the Second SSTUAF32866C (1:2 Register-B Configuration) Device Used in a Pair; C0 = 1, C1 = 1, RESET Switches from L to H NOTES: 1.After RESET is switched from LOW to HIGH, all data and PAR_IN inputs signals must be set and held low for a minimum time of tactmax, to avoid false error. 2.PAR_IN is driven from PPO of the first SSTUAF32866 device. 3.If the data is clocked in on the n clock pulse, the QERR output signal will be generated on the n+2 clock pulse, and it will be valid on the n+3 clock pulse. 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 23 ICSSSTUAF32866C 7100/9 ICSSSTUAF32866C 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Register Timing Timing Diagram for the Second SSTUAF32866C (1:2 Register-B Configuration) Device Used in a Pair; C0 = 1, C1 = 1, RESET Held HIGH NOTES: 1.If the data is clocked in on the n clock pulse, the QERR output signal will be generated on the n+1 clock pulse, and it will be valid on the n+2 clock pulse. If an error occurs and the QERR output is driven low, it stays latched low for a minimum of two clock cycles or until RESET is driven low. 2.PAR_IN is driven from PPO of the first SSTUAF32866 device. 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 24 ICSSSTUAF32866C 7100/9 ICSSSTUAF32866C 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Register Timing RESET tINACT DCS (1) (1) CSR CLK (1) CLK (1) (1) D1 - D14 tRPHL RESET to Q Q1 - Q14 (1) PARIN tRPHL RESET to PPO PPO (not used) QERR tRPLH RESET to QERR H, L, or X H or L Timing Diagram for the First SSTUAF32866C (1:2 Register-A Configuration) Device Used in a Pair; C0 = 1, C1 = 1; RESET Switches from H to L NOTE: 1.After RESET is switched from HIGH to LOW, all data and clock inputs signals must be set and held at valid logic levels (not floating) for a minimum time of tINACTMAX. 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 25 ICSSSTUAF32866C 7100/9 ICSSSTUAF32866C 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Test Circuits and Waveforms (VDD = 1.8V 0.1V) VDD VDD/2 RL = 1K DUT TL = 50 CLK Inputs CLK CLK Test Point RL = 100 Test Point Out CL = 30 pF TL = 350ps, 50 ZO = 50 Test Point Test Point DUT CLK Test Point Out CLK RL = 50 ZO = 50 Test Point RL = 1K CLK Inputs ZO = 50 Production-Test Load Circuit Simulation Load Circuit CLK CLK VICR tPLH Output VTT VICR tPHL VOH VTT VOL VID LVCMOS RESET Input tINACT IDD VDD VDD/2 VDD/2 0V tACT 90% 10% LVCMOS RESET Input Voltage Waveforms - Propagation Delay Times VIH VDD/2 VIL tRPHL VOH Voltage and Current Waveforms Inputs Active and Inactive Times Output VTT VOL tW Input VICR VICR VID Voltage Waveforms - Propagation Delay Times NOTES: 1. CL includes probe and jig capacitance. 2. IDD tested with clock and data inputs held at VDD or GND, and Io = 0mA 3. All input pulses are supplied by generators having the following characteristics: PRR 10MHz, Zo = 50, input slew rate = 1 V/ns 20% (unless otherwise specified). 4. The outputs are measured one at a time with one transition per measurement. 5. VTT = VREF = VDD/2 6. VIH = VREF + 250mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS input. 7. VIL = VREF - 250mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS input. 8. VID = 600mV. 9. tPLH and tPHL are the same as tPDM. Voltage Waveforms - Pulse Duration CLK VICR CLK tSU Input VREF tH VIH VREF VIL VID Voltage Waveforms - Setup and Hold Times 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 26 ICSSSTUAF32866C 7100/9 ICSSSTUAF32866C 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Test Circuits and Waveforms (VDD = 1.8V 0.1V) VDD VDD DUT Out RL = 50 Test Point DUT Out RL = 1K Test Point CL = 10 pF CL = 10 pF Load Circuit: High-to-Low Slew-Rate Adjustment Load Circuit: Error Output Measurements Output 80% VOH LVCMOS RESET Input tPLH VCC VCC/2 0V 20% dv_f dt_f VOL VOH Output Waveform 2 0.15V 0V Voltage Waveforms: High-to-Low Slew-Rate Adjustment Voltage Waveforms: Open Drain Output Low-to-High Transition Time (with respect to RESET input) DUT Out CL = 10 pF Test Point RL = 50 Timing Inputs VICR tHL VICR VI(PP) Output Waveform 1 VCC VCC/2 VOL Load Circuit: Low-to-High Slew-Rate Adjustment Voltage Waveforms: Open Drain Output High-to-Low Transition Time (with respect to clock inputs) dt_r dv_r 80% VOH Timing Inputs VICR tHL VICR VI(PP) VOH 20% Output VOL Output Waveform 2 0.15V 0V Voltage Waveforms: Low-to-High Slew-Rate Adjustment Voltage Waveforms: Open Drain Output Low-to-High Transition Time (with respect to clock inputs) NOTES: 1. CL includes probe and jig capacitance. 2. All input pulses are supplied by generators having the following characteristics: PRR 10MHz, Zo = 50, input slew rate = 1 V/ns 20% (unless otherwise specified). 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 27 ICSSSTUAF32866C 7100/9 ICSSSTUAF32866C 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Test Circuits and Waveforms (VDD = 1.8V 0.1V) DUT Out CL = 5 pF Test Point RL = 1K Load Circuit: Partial-Parity-Out Load Circuit CLK CLK tPLH Output VTT VICR VICR tPHL VOH VTT VOL VI(P-P) Load Circuit: Partial-Parity-Out Voltage Waveforms Propagation Delay Times (with respect to clock inputs) LVCMOS RESET Input VIH VDD/2 VIL tRPHL VOH Output VTT VOL Load Circuit: Partial-Parity-Out Voltage Waveforms Propagation Delay Times (with respect to RESET input) 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 28 ICSSSTUAF32866C 7100/9 ICSSSTUAF32866C 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Package Outline and Package Dimensions - BGA Package dimensions are kept current with JEDEC Publication No. 95 C SEATING PLANE A1 T b REF 4 3 2 1 A B C D Alpha Designations for Vertical Grid (Letters I, O, Q, and S not used) d TYP D1 Numeric Designations for Horizontal Grid D -e- TYP TOP VIEW E h TYP 0.12 C E1 c REF -e- TYP ALL DIMENSIONS IN MILLIMETERS ----- BALL GRID ----Max. T e HORIZ VERT TOTAL d Min/Max Min/Max 13.50 Bsc 5.50 Bsc 1.20/1.40 0.80 Bsc 6 16 96 0.40/0.50 11.50 Bsc 5.00 Bsc 1.00/1.20 0.65 Bsc 6 16 96 0.35/0.45 Note: Ball grid total indicates maximum ball count for package. Lesser quantity may be used. D E h Min/Max 0.25/0.41 0.25/0.35 REF. DIMENSIONS b c 0.75 0.875 0.75 0.875 * Source Ref.: JEDEC Publication 95, 10-0055C MO-205 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 29 ICSSSTUAF32866C 7100/9 ICSSSTUAF32866C 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Ordering Information ICSSSTUAF XX Family XX XXX Device Type Package X Shipping Carrier T Tape and Reel HLF Low Profile, Fine Pitch, Ball Grid Array - Lead-Free 866C 25-Bit Configurable Registered Buffer for DDR2 32 Double Density 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 30 ICSSSTUAF32866C 7100/9 ICSSSTUAF32866C 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Asia Pacific and Japan Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 Europe IDT Europe, Limited Prime House Barnett Wood Lane Leatherhead, Surrey United Kingdom KT22 7DE +44 1372 363 339 (c) 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA |
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